1. Field of the Invention
This invention relates to the field of multiport memories. More particularly, this invention relates to the control of clock signals for driving multiport memories during self-test.
2. Description of the Prior Art
It is known to provide multiport memories having an array of bit storage elements and multiple data access paths permitting multiple concurrent data accesses to be made. These data access paths each have an associated clock signal which drives data accesses on those respective paths. These clock signals are typically asynchronous and independently controlled. An example use of a multiport memory is as a memory shared between two processors with each independently reading data from and writing data to that shared memory using their own data path and with their own clock.
It is important to be able to test memories, including multiport memories, when they are manufactured to ensure that they are free from defects. In order to achieve this, it is known to provide self-test mechanisms, such as built in self-test mechanisms, which write known patterns of data to memories and then read those patterns hack to ensure that they were correctly stored and manipulated. Multiport memories provide a particular challenge in exploring the wide range of situations that can arise during their use. It is known to test such multiple port memories by using the same clock signal driven into the different paths to perform simultaneous data access operations via the different data access paths in an effort to stress the memory and provoke a failure should any defect be present.
This approach suffers from the disadvantage that in a significant number of cases the worst-case scenario is not where the clocks for the different data access paths are exactly the same, but rather where there is a small phase difference between those clocks, as this represents the most challenging situation for the memory. A further problem with the known approach of driving the different data access paths with the same clock signal is that generally the normal operational clock path has to be modified to allow for the insertion of the clock signal taken from another data access path. The clock distribution trees within integrated circuits are normally carefully balanced and subject to considerable effort and expertise in order to operate correctly. Interfering with these clock distribution trees, such as by inserting an additional multiplexer to allow self test using the same clock signal, is a complication that can also compromise non-test operation.
A further known feature of existing memory systems is the use of external memory adjust signals. These external memory adjust signals are provided to allow characteristics of the timing control signals for the memory to be adjusted to achieve higher performance and/or more reliable operation. As an example, the timing characteristics of the memory may be set for operation at a given operational voltage, but the memory may be additionally capable of operating at a different voltage, where different timing relationships would produce better results. The external memory adjust signals allow such changes to be made to the timing characteristics, such as the introduction of additional or shorter delays in the self-timing paths used for controlling memory access operations.